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AeroDAS

Expert-Led Training for Design Assurance and Verification Teams

AeroDAS training is delivered by an expert team with practical experience in aerospace and defense engineering, FPGA development, digital verification, systems engineering, and certification-oriented hardware programs. Programs are designed to help participants connect standards and methods with the engineering decisions, work products, and evidence expected in real projects.

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A whiteboard map of the DO-254 life cycle, linking planning, requirements and traceability, HDL, FPGA and ASIC design, verification and validation, reviews, configuration management, problem reporting, safety, and certification.
The DO-254 life cycle our programs work through, from planning to certification liaison.

Technical Webinar Speakers

AeroDAS provides expert speakers for technical webinars, conferences, professional communities, and internal corporate events.

Sessions can cover DO-254, AMC 20-152A, FPGA design assurance, requirements traceability, verification strategy, SystemVerilog/UVM, simulation-to-HIL workflows, and certification readiness.

Webinars may be delivered as standalone technical sessions, moderated discussions, panel contributions, or customized events for engineering organizations.

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Design Assurance & DO-254 Programs

DO-254 Foundation

Build a clear working understanding of airborne electronic hardware design assurance, life cycle processes, planning, requirements, design, verification, configuration management, process assurance, and certification liaison. Suitable for engineers and stakeholders who need a structured introduction to DO-254 and its practical application.

Certificate awarded: Certificate of Completion

DO-254 Foundation + Assessment

Combine foundational learning with a structured assessment of participant understanding. The program helps organizations identify knowledge gaps and establish a more consistent design assurance vocabulary across engineering, verification, quality, and program teams.

Certificate awarded: Certificate of Completion and Assessment Result

DO-254 Applied Program

Move from awareness to application through guided exercises, project-oriented examples, life cycle-data thinking, traceability scenarios, review questions, and practical readiness activities. The emphasis is on applying design assurance objectives within an engineering program rather than memorizing a standard.

Certificate awarded: Applied Program Completion

Verification Engineering Programs

Basic SystemVerilog / UVM Training

A practical introduction to SystemVerilog and the Universal Verification Methodology for engineers moving toward reusable, coverage-driven verification. Participants develop the core concepts needed to understand testbench architecture, transactions, sequences, drivers, monitors, agents, scoreboards, reference models, functional coverage, and test organization.

Typical learning outcomes

  • Understand the role of SystemVerilog in modern verification environments.
  • Explain the structure and responsibilities of common UVM components.
  • Create and reuse transaction-level stimulus through sequences.
  • Connect monitoring, prediction, checking, and coverage into a coherent verification flow.
  • Read, debug, and extend a basic UVM testbench.

UVM to HIL Training Platform

This practical four-day course demonstrates how to reuse UVM test intent between Questa RTL simulation and an AMD Kria KV260 hardware-in-the-loop target.

Format
Four-day course

Typical learning outcomes

  • Separate verification intent from backend-specific transport.
  • Reuse UVM stimulus, checking, and coverage across simulation and HIL execution.
  • Understand a mixed-language VHDL/SystemVerilog Questa workflow.
  • Connect SystemVerilog to a C++ runtime through a small DPI-C boundary.
  • Evaluate architectural tradeoffs when moving verification intent toward an FPGA-based HIL target.

The synthesizable device under test is written in VHDL-2008. Interfaces, UVM components, tests, and transport classes are written in SystemVerilog, making the simulation flow a deliberate Questa mixed-language example.

Central principle

A test describes what to verify. A transport describes where and how the DUT is reached.

The same packet_item, sequences, reference model, scoreboard, coverage model, and tests are reused with both backends. sim_transport drives SystemVerilog interfaces. hil_transport calls a compact DPI-C API and a C++ runtime.

AeroDAS engineering principle
“Engineering excellence begins where minimum compliance ends.”

AeroDAS training certificates confirm attendance, completion, or assessment results, depending on the selected program. They do not constitute an official regulatory certification or authority approval.